TNETE2008PBE

Product Summary

The TNETE2008PBE OctalPHY is a physical-layer (PHY) interface device for up to eight 10BASE-T networks using a multiplexed medium access controller (MAC) interface. The device operation is fully automatic. It can be taken from reset to full operation without parameter downloads or interaction with a host central processing unit (CPU). The TNETE2008PBE produces and receives IEEE Std 802.3-compliant waveforms when coupled to the network with a suitable transformer. It also incorporates a JTAG-compliant test port.

Parametrics

Absolute maximum ratings over operating junction temperature range: (1)Normal power-supply voltage: 3.3 V ± 5%; (2)DC voltage range applied to logic outputs: –0.05 V to VDDMAX; (3)DC voltage applied to logic input: 3.6 V; (4)DC differential voltage at receiver pins: ±5 V; (5)Input voltage range, VI (see Note 1): –0.5 V to 5.25 V; (6)Operating case temperature range, TC: 0℃ to 95℃; (7)Thermal resistance, junction to ambient, RθJA: 22℃/W; (8)Storage temperature range, Tstg: –65℃ to 150℃.

Features

Features: (1)Single-Chip With Eight Physical-Layer (PHY) Interfaces for Internetworking Applications; (2)Each PHY Is Full-Duplex Capable for Simultaneous Transmit and Receive; (3)Compliant With IEEE Std 802.3 10BASE-T Specification; (4)Integrated Filters on Both Receive and Transmit Circuits: No External Filters Are Required; Meets IEEE Std 802.3 (Section 14.3) Electrical Requirements; (5)Implements IEEE Std 802.3 Autonegotiation to Establish the Highest Common Protocol; (6)Electrostatic Discharge (ESD) Human Body Model (HBM) Protection 1.5 kV Per JEDEC JESD22-A114A; (7)Digital Signal Processor (DSP)-Based Digital Phase-Locked Loop (PLL); (8)Loopback Mode for Test Operations; (9)Integrated Manchester Encoding/Decoding; (10)Receive-Clock Regeneration for All Input Channels Using Digital PLL; (11)FIFOs Accommodate 8x IEEE Limit on Per-Channel-Pair Frequency Mismatch Across All Eight Channels (IEEE Std 802.3, Sec 7.3.2).

Diagrams