SN74AVC16835DGGR

Product Summary

The SN74AVC16835DGGR is a 18-bit universal bus driver with 3-state outputs. A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to TI application reports AVC Logic Family Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC) Circuitry Technology and Applications, literature number SCEA009.

Parametrics

Absolute maximum ratings:(1)Supply voltage range, VCC: –0.5V to 4.6V; (2)Input voltage range, VI: –0.5 V to 4.6 V; (3)Voltage range applied to any output in the high-impedance or power-off state, VO: –0.5 V to 4.6 V; (4)Voltage range applied to any output in the high or low state, VO: –0.5 V to VCC + 0.5 V; (5)Input clamp current, IIK (VI < 0): –50 mA; (6)Output clamp current, IOK (VO < 0): –50 mA; (7)Continuous output current, IO: ±50 mA; (8)Continuous current through each VCC or GND: ±100 mA; (9)Package thermal impedance, θJA (see Note 3): DGG package: 64℃/W; (10)DGV package: 48℃/W; (11)Storage temperature range, Tstg: –65℃ to 150℃.

Features

Features: (1)Member of the Texas Instruments Widebus Family; (2)DOC (Dynamic Output Control) Circuit Dynamically Changes Output Impedance,Resulting in Noise Reduction Without Speed Degradation; (3)Dynamic Drive Capability Is Equivalent to Standard Outputs With IOH and IOL of ±24 mA at 2.5-V VCC; (4)Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications; (5)Ioff Supports Partial-Power-Down Mode Operation; (6)ESD Protection Exceeds JESD 22; (7)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II.

Diagrams